-- Octal Bus Transceiver
-- This example shows the use of the high impedance literal 'Z' provided by std_logic.
-- The aggregate '(others => 'Z')' means all of the bits of B must be forced to 'Z'. 
-- Ports A and B must be resolved for this model to work correctly (hence std_logic rather than std_ulogic). 

library IEEE;   
use IEEE.Std_logic_1164.all;

entity HCT245 is
   port(A, B : inout std_logic_vector(7 downto 0);
         DIR, GBAR : in std_logic);
end HCT245;

architecture VER1 of HCT245 is
begin
   A <= B when (GBAR = '0') and (DIR = '0') else (others => 'Z');
   B <= A when (GBAR = '0') and (DIR = '1') else (others => 'Z');
end VER1;